MUX stands for Multiplexer. It is a combinational circuit that selects binary information from one of many input lines and routes it to one output line. As a result, it is based on many-to-one concepts.MUX is a very important circuit and is widely used in Communication systems, Computer Memory, ALU, Telephone network, etc.
If a market does not have an 8:1 multiplexer and only a 4:1 mux, we can implement 8:1 with only a 4:1 mux and some basic logic gates.
You can easily calculate how much 4:1 MUX is required to make 8:1 MUX. Simply take the numerator section of both muxes. 4 and 8 are examples. Divide the larger by the smaller. ie. 8/4 = 2 and then again divide 2/4 = 0.5.So only 2 4:1 MUX is required and half MUX is not available in the market so we must rely on the NOT gate to operate 0.5 MUX.
- 8/(4 from 4:1 MUX)= 8/4 = 2 again
- 2/(4 from 4:1 MUX) = 2/4 = 0.5 which is decimal. So total = 2 + 0.5 = 2 and half
We'll need two and a half 4-1 multiplexers. As half 4:1 MUX is not available so the notion behind a half multiplexer is really easy; all we have to do is use the enable line for the two multiplexers and enable the first MUX for 4 inputs and disable the next MUX and vice versa.
The total Number of Input Line to implement n:1 MUX is n so in 8:1, the number of input lines = 8
Total Number of Selector required = log28 = 3.
Two 4:1 muxes, an OR gate, and a NOT gate as an enable signal can be used to create an 8:1 multiplexer.
How does it work?
Now let's generate results for each Signal as below
- When signal(S2,S1,S0) are 0 , 0 , and 0 bit then output is first input ie. I0
- When the signal(S2, S1, S0) are 0, 0, and 1 bit then output is second input ie. I1
- When the signal(S2, S1, S0) are 0, 1, and 0 bit then output is third input ie. I2
- When the signal(S2, S1, S0) are 0, 1, and 1 bit then output is the fourth input ie. I3
- When the signal(S2, S1, S0) are 1, 0, and 0 bit then output is fifth input ie. I4
- When the signal(S2, S1, S0) are 1, 0, and 1 bit then output is the sixth input ie. I5
- When the signal(S2, S1, S0) are 1, 1, and 0 bit then output is seventh input ie. I6
- When the signal(S2, S1, S0) are 1, 1, and 1 bit then output is eight inputs ie. I7
Here, S2 is to enable two 4:1 MUX and S2 = 1 selects the outputs from the last four inputs of Second MUX and S2 =0 selects the outputs from the first four inputs.
When S2 = 0 then the first MUX gets enabled with the help of NOT gate the first MUX will get 1 signal at Enable(E) and MUX 1 will be enabled and S2 is applied directly to the second MUX so the second mux received 0 at Enabled(E) so second MUX gets disabled.
When S2 = 1, the first MUX is disabled because the first MUX receives a 0 signal at Enable(E) due to the NOT gate. As a result, MUX 1 is disabled, and S2 is applied directly to the second MUX, so Second MUX gets enabled.
This concludes that only 1 MUX is used at a time. Also, We conclude that at a time only one output is produced.